A phase-locked loop (PLL) is an electronic circuit that generates an output signal whose phase is related to the phase of an input signal. The phase-locked loop comprises a variable frequency oscillator, filter, and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Transmitting the output signal back toward the input signal for comparison is called a feedback loop since the output is “fed back” toward the input forming a loop. An all-digital PLL (ADPLL) uses digital (instead of analog) phase detector, filter and oscillator devices. All digital phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors.
A time-to-digital converter (TDC) is a key building block in all-digital PLL. It is used to measure and quantize a time interval between two input signals to the time-to-digital converter and convert the time interval into a digital (binary) output. The time-to-digital converter may adopt one or more delay lines, each comprising a plurality of delay cells connected in series and used to define the delay time by an input signal propagating through the delay line in the time-to-digital converter. For a time-to-digital converter, the delay cells can be tunable, i.e., the control voltage of the delay cells are controllable so that the timing resolution of the delay lines can be adjusted. Such tunable delay cells are useful for fin field effect transistors (FinFET) used in various different types of semiconductor devices.